Generally, in semiconductor memory devices, a length of write latency and a length of read latency are aligned uniformly, by intentionally delaying the write latency of data. By this uniform alignment, it is possible to eliminate periods (number of free cycles) of not propagating data, on a data line or an interface circuit for commonly propagating data to be read and data to be written. Thus, it enables to lower the number of bus cycles (bus turn around periods) required for switching between a command for writing data and a command for reading data. As a result, it enables to improve processing performance of the semiconductor memory device.
Japanese Unexamined Patent Application Publication No. 2007-66517 discloses, for example, a technique regarding late write (delayed write) for intentionally delaying write latency of data.